Strained semiconductor devices and methods of fabricating strained semiconductor devices

ABSTRACT

A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices;more specifically, it relates to strained semiconductor devices and themethods of fabricating strained semiconductor devices.

BACKGROUND

Strained devices utilize the principle that the mobility of carriers insemiconductor devices can be manipulated by stressing the semiconductormaterial. However, present techniques can result in non-uniform strain.Accordingly, there exists a need in the art to mitigate the deficienciesand limitations described hereinabove.

SUMMARY

A first aspect of the present invention is a structure, comprising: afirst region of a semiconductor substrate separated from a second regionof the semiconductor substrate by trench isolation formed in thesubstrate; a first stressed layer over the first region; a secondstressed layer over second region; the first stressed layer and secondstressed layer separated by a gap; and a passivation layer on the firstand second stressed layers, the passivation layer extending over andsealing the gap.

A second aspect of the present invention is a method, comprising:forming a first region of a semiconductor substrate separated from asecond region of the semiconductor substrate by trench isolation in thesubstrate; forming a first stressed layer over the first region; forminga second stressed layer over second region, the first and secondstressed layers overlapping over the trench isolation; removing theoverlapped first and second stressed layers to form a gap separating thefirst stressed layer from second stressed layer; and forming apassivation layer on the first and second stressed layers, thepassivation layer extending over and sealing the gap.

These and other aspects of the invention are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention are set forth in the appended claims. Theinvention itself, however, will be best understood by reference to thefollowing detailed description of an illustrative embodiment when readin conjunction with the accompanying drawings, wherein:

FIGS. 1 through 7 are cross-sectional views illustrating fabrication ofstrained semiconductor devices according to an embodiment of the presentinvention; and

FIG. 8 is a cross-sectional view of strained devices similar to thoseillustrated in FIG. 7 fabricated in a bulk semiconductor substrate.

DETAILED DESCRIPTION

In n-channel field effect transistors (NFETs), the mobility of themajority carriers, electrons, is greater (hole mobility is less) whenthe channel is in tensile stress in the direction of current flow. Inp-channel field effect transistors (PFETs) the mobility of the majoritycarriers, holes, is greater (electron mobility is less) when the channelregion is in compressive stress in the direction of current flow.Increasing the mobility of majority carriers increases the performanceof the device. Formation of an internally stressed layer over an FETinduces the same type of stress as the overlying stressed layer into thechannel of the FET. Such an FET is termed “a strained device” or“strained FET.”

The embodiments presented herein describe a structure and a methodwhereby oppositely stressed layers are formed on different regions of asemiconductor substrate. The stressed layers induce strain into theunderlying semiconductor substrate. In selected regions, the oppositelystressed layers are spaced apart and do not overlap and do not abut soin the selected regions there is no region where the stresses in thestressed layers are directly opposing each other. However, there may ormay not be other regions of the semiconductor substrate where thestressed layers do overlap.

FIGS. 1 through 7 are cross-sectional views illustrating fabrication ofstrained semiconductor devices according to an embodiment of the presentinvention. In FIG. 1, a silicon-on-insulator (SOI) substrate 100includes an upper semiconductor layer 105 separated from a lowersupporting substrate 110 by a buried oxide layer 115. In one example,upper semiconductor layer 105 is single-crystal silicon. Formed in uppersubstrate 105 is trench isolation 120. A top surface 122 of trenchisolation 120 is coplanar with a top surface 123 of semiconductor layer105. Trench isolation 120 extends to abut buried oxide layer 115. In oneexample, trench isolation 120 is formed, by etching (e.g., by reactiveion etch (RIE)) a trench into semiconductor layer using a patternedphotoresist layer as an etch mask, removing the photoresist, depositingan insulating layer to overfill the trench and then performing achemical-mechanical-polish (CMP) to coplanarize the top surface 122 ofthe trench isolation 120 and the top surface 123 of semiconductor layer105. In one example, trench isolation 120 comprises silicon oxide(SiO₂).

Next an n-channel field effect transistor (NFET) 125A is formed in aregion 127 of substrate 100 and a p-channel field effect transistor(PFET) 125B is formed in a region 128 of substrate 100. Regions 127 and128 are separated by a region trench isolation 120. NFET 125A includesN-type source/drains 130A separated by a P-type channel region 135Aunder a gate electrode 140A. Gate electrode 140A is electricallyisolated from source/drains 130A and channel region 135A by a gatedielectric layer 145A. Insulating sidewall spacers 150A are formedopposite side walls of gate electrode 140A. PFET 125B includes P-typesource/drains 130B separated by an N-type channel region 135B under agate electrode 140B. Gate electrode 140B is electrically isolated fromsource/drains 130B and channel region 135B by a gate dielectric layer145B. Insulating sidewall spacers 150B are formed opposite side walls ofgate electrode 140B.

In one example, sidewall spacers 150A and 150B comprise silicon nitride(Si₃N4), SiO₂ or combinations of layers thereof. In one example, gateelectrodes 140A and 140B comprise doped or undoped polysilicon.

In FIG. 2, a dielectric tensile stressed layer 155 is formed over NFET125A, PFET 125B and trench isolation 120. In one example, tensilestressed layer 155 is Si₃N₄. In one example, a tensile stressed Si₃N₄layer is formed by low-pressure chemical vapor deposition (LPCVD) usingsilane (SiH₄) and ammonia (NH₃) precursor gases. In one example, atensile stressed layer 155 is between about 50 nm and about 100 nmthick. In one example, the amount of tensile stress applied to NFET 125Aby tensile stressed layer 155 is between about 0.5 GPa and about 4 GPa.

In FIG. 3, tensile stressed layer 155 is removed from over PFET 125Busing a photolithographic/etch process. For example, a patternedphotoresist layer is formed over tensile stressed layer 155 and thetensile stressed layer etched, for example, using RIE, where the tensilestressed layer is not covered by the patterned photoresist layer,followed by removal of the patterned photoresist layer. In FIG. 3,tensile stressed layer overlaps a region of trench isolation 120 betweenNFET 125A and PFET 125B. Tensile stressed layer 155 does not overlap anyregion of PFET 125B.

In FIG. 4, a dielectric compressive stressed layer 160 is formed overPFET 125B, trench isolation 120 and remaining portions of tensilestressed layer 155. In one example, compressive stressed layer 160 isSi₃N₄. In one example, a compressive stressed Si₃N₄ layer is formed byhigh density plasma (HDP) deposition or plasma enhanced chemical vapordeposition (PECVD) using SiH₄, NH₃ and nitrogen (N₂) precursor gases. Inone example, a compressive stressed layer 160 is between about 60 nm andabout 120 nm thick. In one example, the amount of compressive stressedapplied to PFET 125B by compressive stressed layer 160 is between about0.5 GPa and about 4 GPa.

In FIG. 5, compressive stressed layer 160 is removed from over NFET 125Ausing a photolithographic/etch process. For example, a patternedphotoresist layer is formed over compressive stressed layer 160 and thecompressive stressed layer etched, for example, using RIE, where thecompressive stressed layer is not covered by the patterned photoresistlayer, followed by removal of the patterned photoresist layer. In FIG.5, compressive stressed layer 160 overlaps a region of trench isolation120 between NFET 125A and PFET 125B. Compressive stressed layer 160overlaps tensile stressed layer 155 in an overlap region 165.Compressive stressed layer 160 does not overlap any region of NFET 125A.Overlap region 165 does not extend over NFET 125A or PFET 125B.

It should be understood though tensile stressed layer 155 has beenillustrated as being formed and etched before forming compressedstressed layer 160, alternatively compressed stressed layer 160 beformed and etched before forming tensile stressed layer 155. This wouldresult in tensile stressed layer 155 being on top of compressivestressed layer 160 in overlap region 165.

In FIG. 6, tensile stressed layer 155 and compressive stressed layer 160have been removed in overlap region 165 (see FIG. 5) using aphotolithographic/etch process to form a gap 170 between tensilestressed layer 125A and compressive stressed layer 160. For example, apatterned photoresist layer is formed over tensile stressed layer 155and compressive stressed layer 160 and the tensile and compressivestressed layers etched, for example, using RIE, where the compressivestressed layer is not covered by the patterned photoresist layer (i.e.,in overlap region 165 of FIG. 5), followed by removal of the patternedphotoresist layer. Trench isolation 120 is exposed in gap 170 and gap170 is fully landed (i.e., does not extend over any regions of siliconlayer 105) on trench isolation 120.

Because tensile stressed layer 155 and compressive stressed layer 160are not overlapped and because tensile stressed layer 155 does not abutcompressive stressed layer 160 due to gap 170, the stressed induced intoNFET 125A is only due to tensile stressed layer 155 and is notinfluenced by compressive stressed layer 160. Because tensile stressedlayer 155 and compressive stressed layer 160 are not overlapped andbecause tensile stressed layer 155 does not abut compressive stressedlayer 160 due to gap 170, the stressed induced into PFET 125B is onlydue to compressive stressed layer 160 and is not influenced by tensilestressed layer 155. Further the stress induced in the semiconductorregions of NFET 125A and PFET 125B is more uniform as the effect ofoverlapped stress layers on the underlying substrate is highestproximate to the overlapped region and diminishes with distance.

In FIG. 7, a passivation layer 170 is formed over tensile stressed layer155, compressive stressed layer 160 and trench isolation 120 in gap 170.Passivation layer 175 seals the gap and prevents contaminants enteringNFET 125A or PFET 125B by diffusion through trench isolation 120 intosilicon layer 105. In one example, passivation layer 175 is unstressed.In one example, passivation layer 175 is in a compressive stress lessthan that of compressive stressed layer 160. In one example, passivationlayer 175 is in a tensile stress less than that of tensile stressedlayer 155. In one example, passivation layer 175 is unstressed Si₃N₄. Inone example, passivation layer 175 is Si₃N₄ in a compressive stress lessthan that of compressive stressed layer 160. In one example, passivationlayer 175 is Si₃N₄ in a tensile stress less than that of tensilestressed layer 155. It is preferred that the amount of stress inpassivation layer 175 (whether compressive or tensile) be as low aspossible. In one example, passivation layer 175 is a Si₃N₄ layer whichis formed by high density plasma (HDP) deposition or plasma enhancedchemical vapor deposition (PECVD) using SiH₄, NH₃ and nitrogen (N₂)precursor gases. In one example, a passivation layer is between about 20nm and about 40 nm thick.

FIG. 8 is a cross-sectional view of strained devices similar to thoseillustrated in FIG. 7 fabricated in a bulk semiconductor substrate. InFIG. 8, an NFET 125C and a PFET 125D have been fabricated in a bulksemiconductor substrate 180. In one example, substrate 180 issingle-crystal silicon. NFET 125C is similar to NFET 125A exceptsource/drains 130A and channel region 135A are formed in a P-well 185.PFET 125D is similar to PFET 125B except source/drains 130B and channelregion 135B are formed in an N-well 190.

Thus the embodiments of the present invention provide more uniformlystrained semiconductor devices by eliminating the overlap of differentlystressed films in selected regions of the integrated circuit chip.

The description of the embodiments of the present invention is givenabove for the understanding of the present invention. It will beunderstood that the invention is not limited to the particularembodiments described herein, but is capable of various modifications,rearrangements and substitutions as will now become apparent to thoseskilled in the art without departing from the scope of the invention.Therefore, it is intended that the following claims cover all suchmodifications and changes as fall within the true spirit and scope ofthe invention.

1. A structure, comprising: a first region of a semiconductor substrateseparated from a second region of said semiconductor substrate by trenchisolation formed in said substrate; a first stressed layer over saidfirst region; a second stressed layer over second region; said firststressed layer and second stressed layer separated by a gap; and apassivation layer on said first and second stressed layers, saidpassivation layer extending over and sealing said gap.
 2. The structureof claim 1, wherein said gap is formed over a region of said trenchisolation.
 3. The structure of claim 1, wherein said first stressedlayer is in tensile stress and said second stressed layer is incompressive stress.
 4. The structure of claim 1, wherein said firststressed layer is silicon nitride in tensile stress and said secondstressed layer is silicon nitride in compressive stress.
 5. Thestructure of claim 1, wherein said passivation layer is silicon nitride.6. The structure of claim 1, further including: first source/drains onopposite sides of a first channel region formed in said first region anda first gate electrode formed over said first channel region; and secondsource/drains on opposite sides of a second channel region formed insaid second region and a second gate electrode formed over said secondchannel region.
 7. The structure of claim 6, wherein said firstsource/drains, said first channel region and said first gate electrodecomprise an NFET and said first source/drains, said first channel regionand said first gate electrode comprise a PFET; and wherein said firststressed layer is silicon nitride in tensile stress and said secondstressed layer is silicon nitride in compressive stress.
 8. Thestructure of claim 6, wherein said first stressed layer extends oversaid first gate electrode and said first source/drains and said secondstressed layer extends over said second gate electrode and said secondsource/drains.
 9. The structure of claim 6, wherein said passivationlayer is silicon nitride.
 10. The structure of claim 6, wherein saidsemiconductor substrate comprises a silicon layer separated from asilicon substrate by a buried oxide layer and said first source/drains,said first channel region, said second source/drains, said secondchannel region and said trench isolation are formed in said siliconlayer.
 11. A method, comprising: forming a first region of asemiconductor substrate separated from a second region of saidsemiconductor substrate by trench isolation in said substrate; forming afirst stressed layer over said first region; forming a second stressedlayer over second region, said first and second stressed layersoverlapping over said trench isolation; removing said overlapped firstand second stressed layers to form a gap separating said first stressedlayer from second stressed layer; and forming a passivation layer onsaid first and second stressed layers, said passivation layer extendingover and sealing said gap.
 12. The method of claim 11, wherein said gapis formed over a region of said trench isolation.
 13. The method ofclaim 11, wherein said first stressed layer is in tensile stress andsaid second stressed layer is in compressive stress.
 14. The method ofclaim 11, wherein said first stressed layer is silicon nitride intensile stress and said second stressed layer is silicon nitride incompressive stress.
 15. The method of claim 11, wherein said passivationlayer is silicon nitride.
 16. The method of claim 11, further including:before forming said first stressed layer or said second stressed layer,forming first source/drains on opposite sides of a first channel regionformed in said first region and forming a first gate electrode over saidfirst channel region; and before forming said first stressed layer orsaid second stressed layer, forming second source/drains on oppositesides of a second channel region formed in said second region andforming a second gate electrode formed over said second channel region.17. The method of claim 16, wherein said first source/drains, said firstchannel region and said first gate electrode comprise an NFET and saidfirst source/drains, said first channel region and said first gateelectrode comprise a PFET; and wherein said first stressed layer issilicon nitride in tensile stress and said second stressed layer issilicon nitride in compressive stress.
 18. The method of claim 16,wherein said first stressed layer extends over said first gate electrodeand said first source/drains and said second stressed layer extends oversaid second gate electrode and said second source/drains.
 19. The methodof claim 16, wherein said passivation layer is silicon nitride.
 20. Themethod of claim 16, wherein said semiconductor substrate comprises asilicon layer separated from a silicon substrate by a buried oxide layerand said first source/drains, said first channel region, said secondsource/drains, said second channel region and said trench isolation areformed in said silicon layer.